Integrated circuits incorporating system-on-a-chip (SoC) technology integrate many distinct components into a single chip. Such components may include microcontrollers, microprocessors, digital signal processing (DSP) cores, memory blocks, and others. Each of these components may include a clock network to synchronize logic and control thereof.
Typically a plurality of edge-triggered flip-flops, such as master-slave D-type flip-flops, are used in the data paths of an integrated circuit triggered by a rising edge or a falling edge of a clock signal in the clock tree network. The plurality of edge-triggered flip-flops are typically used in integrated circuits to propagate data from a source element to one or more target elements. Generally, the propagation of data is performed synchronously with a periodic clock signal generated by a clock source. A clock tree network is typically employed to route the clock signal to the clock input of the flip-flops in a manner that delay, skew and slew are within the specification for the integrated circuit.
For each triggering edge of the periodic clock signal, the edge-triggered flip-flops propagate data from an input to an output. During the triggering edge of the clock signal, a large number of flip-flops may change state at substantially the same time so that a greater level of power may be consumed in order to effectuate the propagation and evaluation of data. This power is part of the dynamic power used by the integrated circuit. With wider data paths being used in integrated circuits, additional power may be consumed by the larger number of parallel flip flops used to make up each register therein. The clock tree network typically consumes a portion of the dynamic power in an integrated circuit. This is because the clock signals are typically periodically switched over a high level of capacitance in the clock wiring network by large clock buffers.
Generally, designers of integrated circuits are often developing techniques to reduce the dynamic power consumed by the clock network. Prior techniques developed for reducing the dynamic power of the clock network include using smaller clock buffers, reducing the overall wiring capacitance, clock gating to reduce the dynamic power at a particular instance, and using techniques, such as de-cloning, to move the clock buffers at higher levels of the clock hierarchical network. However, even with these techniques, the dynamic power of an integrated circuit can be further reduced.
One type of edge-triggered flip-flop is a D type flip-flop (“D flip-flop”) that is triggered by a rising edge or falling edge of a clock signal. FIG. 12 illustrates an exemplary rising edge-triggered fully complimentary metal oxide semiconductor (CMOS) D type flip-flop 1200. The CMOS D flip-flop 1200 has a master portion including transfer gates formed of transistors 1210N and 1210P, transistors 1211N and 1211P, and inverters 1212A and 1212B; and a slave portion including transfer gates formed of transistors 1220N and 1220P, transistors 1221N and 1221P, and inverters 1222A and 1222B for a total of sixteen transistors. The eight transistors in the inverters 1212A and 1212B, and 1222A and 1222B in the D flip-flop 1200 are active and consume power. The inverter 1203 that inverts the clock signal CLK may be used by the D flip-flop as well as a latch and may be external to each so it is shared by other circuits and is therefore not counted.
A latch in comparison to a D flip-flop consumes less dynamic power as it has fewer transistors to switch. An inverting fully complementary metal oxide semiconductor (CMOS) latch has a total of eight transistors, four of which are active to consume power. Thus, an inverting CMOS latch may consume half of the power of a CMOS D flip-flop. Additionally, a CMOS latch may use less silicon area than a CMOS D flip-flop. Accordingly, an integrated circuit that uses latches in place of some of its flip-flops can consume less power. However, there are design issues with replacing an edge-triggered flip-flop with a latch. A circuit design system that assists a designer in properly implementing a replacement of at least some of the edge-triggered flip-flops in a circuit design with latches would be of substantial value.